Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor memory device including double bit lines and a method for fabricating the semiconductor memory device.
A semiconductor memory device such as a Dynamic Random Access Memory (DRAM) device includes a plurality of banks, where each bank includes a plurality of mats (that is, matrixes) and a plurality of sense amplifier regions. Here, each mat includes a plurality of word lines and a plurality of bit lines, and each sense amplifier region includes a plurality of sense amplifiers (SA), each of which is coupled with a bit line extending from a mat and detects a stored data. The structure of bit lines are divided into a folded bit line structure and an open bit line structure depending on different ways that a bit line is coupled with a sense amplifier. As the integration degree of a semiconductor memory device increases, the open bit line structure is being used more extensively.
A sense amplifier may be coupled with two bit lines, which include a main bit line BL and a line /BL. While a sense amplifier operates, a reference voltage may be applied to the secondary bit line /BL and a data voltage higher or lower than the reference voltage is applied to the main bit line according to the data stored in a corresponding mat. Here, the sense amplifier reads the stored data by amplifying the voltage difference between the main bit line and the secondary bit line.
However, in a conventional semiconductor memory device having the open bit line structure, a main bit line and a secondary bit line coupled with a sense amplifier are supplied from different mats. Therefore, the reference voltage applied to the secondary bit line is changed due to the noise applied to each mat, and this leads to deteriorated operation characteristics of the sense amplifier.
Also, each of the mats of a semiconductor memory device includes a redundancy mat. Since the main bit line and the secondary bit line are supplied from different mats in the open bit line structure, only half of a redundancy mat is actually used. Thus, a method for increasing the utility efficiency based on the area of a redundancy mat even if the size of banks is decreasing and the number of banks is increasing to realize high-speed operation is useful.